System Verilog Clocking block -


i trying perform simple test demo code of clocking block, encountered error.

the code find @ "eda playground" http://www.edaplayground.com/x/3ga

and error says: ** error: testbench.sv(38): default clocking block must specified use ##n timing statement. ** error: testbench.sv(40): default clocking block must specified use ##n timing statement.

i think clocking block has been specified in code.

any help?

as error message says, have define clocking block default: 

default clocking cb_counter @(posedge clock);

full code here: http://www.edaplayground.com/x/37_

the sv 2012 standard specifies ##n operator can used if there default clocking block defined module/program/interface, otherwise wouldn't able know clock event use delay.


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