verilog - Systemverilog dynamic casting issues -


i've code snippet following in testbench

function void write_to_port( my_data_type_base data );     my_data_type_extended data_ext;     if(!$cast(data_ext, data));         `uvm_error(get_type_name(), "failed cast");    `uvm_info(get_name(), $psprintf("data_ext :\n%s", data_ext.sprint()), uvm_medium)   // write data_ext out port.... endfunction

when run it, i'm getting uvm_error "failed cast." i'm not quire sure why $cast not returning 1. can see, i'm printing out extended class data item after casting uvm_info. can see it's being cast properly. if don't use $cast if condition, don't runtime error. isn't coding practice use if dynamic cast check if $cast returning 1 ?

what might reason behind cast not returning 1 in above case?

i think semicolon on line 'if' not belong?

i think consumes if statement, , uvm_error executes regardless of how if evaluates:

if(!$cast(data_ext, data)); <- no semicolon     `uvm_error(get_type_name(), "failed cast");

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