Makefile: Wildcard for two programs with different source files -


i'm working on c project 2 programs, server , client.
projects structure:

. +--/bin |  +--/client |  +--/server | +--/lib |  +--header1.h |  +--header2.h |  +--header3.h | +--/obj |  +--/client |  +--/server | +--/src |  +--/client |  |  +--files.c |  +--/server |     +--otherfiles.c | +--makefile

now i'm stuck on makefile, both programs need different , overlapping headers. tried looking other projects/repositories, didn't me.
got:

sources_client = ${wildcard src/client/files.c} sources_server = ${wildcard src/client/otherfiles.c}  headers_client = ${wildcard lib/header1.h lib/header2.h} headers_server = ${wildcard lib/header2.h lib/header3.h}  obj_client = ${sources_client:.c=.o} obj_server = ${sources_server:.c=.o}  cc = gcc cflags = #not relevant  all: client server  client: ${obj_client}     ${cc} -o $@ $^  server: ${obj_server}     ${cc} -o $@ $^

how create wildcard rules convert source files object files (in correct bin/ directory) using corresponding header files? makefile seems optimizable, if how?

i suppose base variable definitions must more this:

sources_client = ${wildcard src/client/*.c} sources_server = ${wildcard src/server/*.c}  headers_client = ${wildcard lib/client*.h} headers_server = ${wildcard lib/server*.h}

one of first things need understand make knows nothing build tools, directories, or files. manipulates strings, , chooses subset of strings works , forms issue shell commands, timing , order governed ruleset expressed it.

among implications if want build given target have write rule exactly target. in particular, when run make root directory of project, wanted binaries (in scheme) not client , server, bin/client , bin/server. similarly, wanted object file corresponding src/client/files.c not files.o or src/client/files.o rather obj/client/files.o.

having understood that, next order of business define object file lists correctly. seem committed gnu make already, makes things easier (at cost in portability). instead of current definitions obj_client , obj_server, provide object files in different location require, using (gnu-specific) substitution reference work:

obj_client = $(sources_client:src/client/%.c=obj/client/%.o) obj_server = $(sources_server:src/server/%.c=obj/server/%.o)

having done that, however, you'll need write explicit rules building object files; make's default rules not handle needed cross-directory correspondence. can use gnu pattern rules purpose. introduce dependencies on headers:

obj/client/%.o: src/client/%.c $(headers_client)     $(cc) $(cppflags) $(cflags) -c $< -o $@

again taking account fact must provide build rules naming targets want build, might put as:

sources_client = $(wildcard src/client/*.c) sources_server = $(wildcard src/server/*.c)  headers_client = $(wildcard lib/client*.h) headers_server = $(wildcard lib/server*.h)  obj_client = $(sources_client:src/client/%.c=obj/client/%.o) obj_server = $(sources_server:src/server/%.c=obj/server/%.o)  cc = gcc cflags = #not relevant  all: bin/client bin/server  bin/client: $(obj_client)     $(cc) $(cflags) -o $@ $^  bin/server: $(obj_server)     $(cc) $(cflags) -o $@ $^  obj/client/%.o: src/client/%.c $(headers_client)     $(cc) $(cppflags) $(cflags) -c $< -o $@  obj/server/%.o: src/server/%.c $(headers_server)     $(cc) $(cppflags) $(cflags) -c $< -o $@

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