cpu - How does Memory Controller distributes the data to DIMMs? -


a hypothetical scenario when computer has 2 dimms, how memory controller distributes data between two?

it has use bits address, bits , why bits.

i per dimm bank/row size make sense, since have big number of concurrently valid rowbuffers , may increase bandwidth.

how done? (let's assume common cpu architecture on x86)

here presents results based on experiments intel sandy bridge cpus:

bits 0-5: these lower 6 bits of byte index within row (i.e. 6-bit index 64-byte cache line).

bit 6: 1-bit channel number, selects between 2 dimms.

bits 7-13: these upper 7 bits of index within row (i.e. upper bits of column number). bits 14-16: these xor'd bottom 3 bits of row number give 3-bit bank number.

bit 17: 1-bit rank number, selects between 2 ranks of dimm (which typically 2 sides of dimm's circuit board).

bits 18-32: these 15-bit row number.

bits 33+: these may set because physical memory starts @ physical addresses greater 0.


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