gpgpu - Latency to/from Xeon Phi -


what typical latency measure moving "small amount" of data (like few kb) cpu cache coprocessor xeon phi? assume return trip take similar amount of time, if not, please specify in answer.

i know depends on lot of things, i'm looking order-of-magnitude numbers, , don't have similar setup test.

i'm afraid question, ask doesn't have answer. can ask raw bandwidth , latency of pcie bus is, doesn't tell anything. , wouldn't want read word cache in processor sending coprocessor. want keep processor out of as possible. @ minimum, need know before can ask question protocol using move data, data , how big data transfer. suggest read intel® xeon phi™ coprocessor system software developers guide if want know intel xeon phi coprocessor in particular. (i can't speak other architectures - i'm ignorant there.) system software developers guide way more detail want or need @ point. if want general idea of going on, tell intel xeon phi coprocessor uses called scif communicate between host , coprocessor , can find out basics in chapter 6 of rezaur's book intel® xeon phi™ coprocessor architecture , tools: guide application developers (which can find on google books if want read chapter.) say, can't speak other architecture; don't know. i'm sure can find information out there.


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