Simulation error in verilog in modelsim ACTEL6.6d -

i new verilog, trying compile basic code found on stackoverflow (simulation error in verilog). design block

module inst_line_buffer(input wire [511:0]from_ls,                     input wire clk,                     output reg [63:0]to_if_id); parameter mem_size=16; integer k;     reg [31:0] ilb[0:mem_size-1];     initial  begin   (k = 0; k < mem_size ; k = k + 1)     begin     ilb[k] = 32'b00;     //$display ("ilb= %b",ilb[k]);     end  end  @(posedge clk)    begin    ilb[0]= from_ls[511:480];    ilb[1]= from_ls[479:448];    ilb[2]= from_ls[447:416];    ilb[3]= from_ls[415:384];    ilb[4]= from_ls[383:352];    ilb[5]= from_ls[351:320];    ilb[6]= from_ls[319:288];    ilb[7]= from_ls[287:256];    ilb[8]= from_ls[255:224];    ilb[9]= from_ls[223:192];    ilb[10]= from_ls[191:160];    ilb[11]= from_ls[159:128];    ilb[12]= from_ls[127:96];    ilb[13]= from_ls[95:64];    ilb[14]= from_ls[63:32];    ilb[15]= from_ls[31:00];    to_if_id [63:32]= ilb[0];    to_if_id [31:0]= ilb[1];    $display("ilb= %b", ilb[1]);   end endmodule 

my testbench :

module testbench; reg [511:0]from_ls; reg clk; reg [63:0]to_if_id;  inst_line_buffer inst_line_buffer (     .from_ls    (from_ls),     .clk        (clk),     .to_if_id   (to_if_id) );   initial  begin   clk= 0;   to_if_id[63:0]=63'b0;   from_ls[511:480]= 32'b00011_00000_00100_01100_11100_10111_01;   from_ls[479:448]=32'b00_11000_00100_01111_11111_00011_10000;  end  begin   #10 clk= ~ clk;    //from_ls[511:448]= ~ from_ls[511:448];   $display("from_ls= %b", from_ls);   $display("to_if_id= %b", to_if_id);  end endmodule 

there no compilation error. when try simulate testbench, following error:

loading work.testbench loading work.inst_line_buffer ** error: (vsim-3053) c:/actel/libero_v9.1/model/design_tb.v(9): illegal output or inout port connection "port 'to_if_id'". region: /testbench/inst_line_buffer error loading design 

can me this? in advance.

in testbench to_if_id should declared wire. since output component, there no need declare reg. don't forget remove signal initial block.